UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 915

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

17.16
The following shows three operation procedures with the flowchart.
(1) Master operation in single master system
(2) Master operation in multimaster system
(3) Slave operation
The flowchart when using the V850E/IF3 and V850E/IG3 as the master in a single master system is shown
below.
This flowchart is broadly divided into the initial settings and communication processing. Execute the initial
settings at startup. If communication with the slave is required, prepare the communication and then execute
communication processing.
In the I
specifications when the bus takes part in a communication. Here, when data and clock are at a high level for a
certain period (1 frame), the V850E/IF3 and V850E/IG3 take part in a communication with bus released state.
This flowchart is broadly divided into the initial settings, communication waiting, and communication processing.
The processing when the V850E/IF3 and V850E/IG3 lose in arbitration and are specified as the slave is
omitted here, and only the processing as the master is shown. Execute the initial settings at startup to take
part in a communication. Then, wait for the communication request as the master or wait for the specification
as the slave. The actual communication is performed in the communication processing, and it supports the
transmission/reception with the slave and the arbitration with other masters.
An example of when the V850E/IF3 and V850E/IG3 are used as the slave is shown below.
When used as the slave, operation is started by an interrupt. Execute the initial settings at startup, then wait
for the INTIIC interrupt occurrence (communication waiting).
communication status is judged and its result is passed as a flag over to the main processing.
By checking the flags, necessary communication processing is performed.
Communication Operations
2
C bus multimaster system, whether the bus is released or used cannot be judged by the I
User’s Manual U18279EJ3V0UD
CHAPTER 17 I
2
C BUS
When the INTIIC interrupt occurs, the
2
C bus
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