UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 625

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(1) A/D converter n scan mode register (ADnSCM)
The ADnSCM register is a register that specifies the normal operation mode and controls conversion
operations.
This register can be read or written in 16-bit units.
When the higher 8 bits of the ADnSCM register are used as the ADnSCMH register and the lower 8 bits, as the
ADnSCML register, these registers can be read or written in 1-bit or 8-bit units. However, bit 14 is read-only.
Reset sets this register to 0000H.
ADnSCM
(n = 0, 1)
After reset: 0000H
Note 1. When using A/D converters 1 and 0, be sure to set bit 1 to "1".
Notes 2. The ADnCS bit is set to 1 five basic clocks (f
<15> 14
ADn
CE
ADnPLM
ADnCE
ADnCS
ADnPS
0
1
0
1
0
0
1
0
1
ADn
CS
Other than above
3. In the extended operation mode (conversion channel specification mode or
This setting can be performed at the same time as other ADnSCM register bits.
ADnTRG1
13
Stop conversion operation
Start conversion operation
A/D conversion stopped
A/D conversion operating
(remains “1” even when the channel is changed during successive
conversion)
A/D power save mode
A/D operational mode
R/W
to 1 and A/D conversion has been started.
A/D conversion is started when a trigger signal, such as one from a timer, is input in
the hardware trigger mode, conversion channel specification mode, or extension
buffer mode. In the A/D trigger mode and A/D trigger polling mode, it is started
when the ADnCE bit is 1.
extension buffer mode), be sure to set the hardware trigger mode.
0
0
0
0
12
0
CHAPTER 12 A/D CONVERTERS 0 AND 1
Address: AD0SCM FFFFF220H, AD1SCM FFFFF2A0H
ADnTRG0
11
0
0
1
0
PLM
ADn
10
User’s Manual U18279EJ3V0UD
A/D power save mode specification
TRG1
A/D conversion operation control
ADn
Status of A/D converter n
9
A/D trigger mode
Hardware trigger mode
A/D trigger polling mode
Setting prohibited
TRG0
ADn
8
Normal operation mode specification
ADn
PS
7
6
0
5
0
Note 3
Note 2
4
0
AD01
3
0
) after the ADnCE bit has been set
2
0
0
1
Note 1
0
0
(1/2)
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