UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 65

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

3.2.2
load/store instruction (LDSR or STSR instruction).
Register No.
System registers control the status of the CPU and hold interrupt information.
To read/write these system registers, specify a system register number indicated below using the system register
Notes 1.
Caution Even if bit 0 of EIPC, FEPC, or CTPC is set to 1 by the LDSR instruction, bit 0 will be ignored
Remark
21 to 31
System
6 to 15
16
17
18
19
20
0
1
2
3
4
5
System register set
2.
when the program is returned by the RETI instruction after interrupt servicing (because bit 0 of
the PC is fixed to 0). When setting the value of EIPC, FEPC, and CTPC, use an even value (bit 0 =
0).
√: Access allowed
×: Access prohibited
Because this register has only one set, to enable multiple interrupts, it is necessary to save this register
by program.
These registers can be read/written only in the period between DBTRAP instruction or illegal opcode
execution and DBRET instruction execution.
Interrupt status saving register (EIPC)
Interrupt status saving register (EIPSW)
NMI status saving register (FEPC)
NMI status saving register (FEPSW)
Interrupt source register (ECR)
Program status word (PSW)
Reserved for future function expansion (operations that access these
register numbers cannot be guaranteed).
CALLT execution status saving register (CTPC)
CALLT execution status saving register (CTPSW)
Exception/debug trap status saving register (DBPC)
Exception/debug trap status saving register (DBPSW)
CALLT base pointer (CTBP)
Reserved for future function expansion (operations that access these
register numbers cannot be guaranteed).
System Register Name
Table 3-2. System Register Numbers
CHAPTER 3 CPU FUNCTION
User’s Manual U18279EJ3V0UD
Note 1
Note 1
LDSR Instruction
√
√
Note 2
Note 2
Operand Specification
√
√
√
√
×
√
×
√
√
√
×
STSR Instruction
√
√
Note 2
Note 2
√
√
√
√
√
√
×
√
√
√
×
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