UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 746

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

744
Therefore, the maximum baud rate that can be received by the destination is as follows.
Similarly, obtaining the following maximum allowable transfer rate yields the following.
Therefore, the minimum baud rate that can be received by the destination is as follows.
Obtaining the allowable baud rate error for UARTAn and the destination from the above-described equations for
obtaining the minimum and maximum baud rate values yields the following.
Remarks 1. The reception accuracy depends on the bit count in 1 frame, the input clock
4
8
20
50
100
255
Division Ratio (k)
10
11
BRmax = (FLmin/11)
BRmin = (FLmax/11)
× FLmax = 11 × FL −
FLmax =
2. k: Set value of UAnCTL2.UAnBRS7 to UAnCTL2.UAnBRS0 bits (n = 0 to 2)
CHAPTER 14 ASYNCHRONOUS SERIAL INTERFACE A (UARTA)
Table 14-4. Maximum/Minimum Allowable Baud Rate Error
frequency, and the division ratio (k). The higher the input clock frequency
and the larger the division ratio (k), the higher the accuracy.
21k − 2
Maximum Allowable Baud Rate Error
20 k
−
−
1
1
=
FL × 11
=
k + 2
2 × k
21k − 2
21k + 2
20k
22k
User’s Manual U18279EJ3V0UD
+2.32%
+3.52%
+4.26%
+4.56%
+4.66%
+4.72%
× FL =
Brate
Brate
21k − 2
2 × k
FL
Minimum Allowable Baud Rate Error
−2.43%
−3.61%
−4.30%
−4.58%
−4.67%
−4.72%