UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 41

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(2) Internal units
(a) CPU
(b) Bus control unit (BCU)
(c) ROM
(d) RAM
The CPU uses five-stage pipeline control to enable single-clock execution of address calculations,
arithmetic logic operations, data transfers, and almost all other instruction processing.
Other dedicated on-chip hardware, such as a multiplier (32 bits × 32 bits → 64 bits) and a barrel shifter (32
bits), help accelerate complex processing.
The BCU starts the required external bus cycles in accordance with the physical address obtained by the
CPU. If the CPU does not request the start of a bus cycle when an instruction is fetched from the external
memory area (
address and prefetches an instruction code. The prefetched instruction code is loaded to the internal
instruction queue.
The BCU controls a memory controller (MEMC) and performs external memory access (
8EA-A and 70F3454F1-DA9-A only).
(i) Memory controller (MEMC) (
(ii) DMA controller (DMAC)
This is flash memory that is mapped from address 00000000H.
During instruction fetch, ROM/flash memory can be accessed from the CPU in 1-clock cycles. The
internal ROM capacity and area differ as follows depending on the product.
The internal RAM capacity and area differ as follows depending on the product.
During instruction fetch or data access, data can be accessed from the CPU in 1-clock cycles.
μ
μ
μ
μ
PD70F3453
PD70F3454
PD70F3453
PD70F3454
Controls access to SRAM, external ROM, and external I/O.
This controller controls data transfer between on-chip peripheral I/O and internal RAM or on-chip
peripheral I/O and on-chip peripheral I/O instead of the CPU.
The transfer type is two-cycle transfer, and single transfer, single-step transfer, and block transfer are
used in transfer mode.
Part Number
Part Number
μ
PD70F3454GC-8EA-A and 70F3454F1-DA9-A only), the BCU generates a prefetch
CHAPTER 1 INTRODUCTION
μ
PD70F3454GC-8EA-A and 70F3454F1-DA9-A only)
User’s Manual U18279EJ3V0UD
128 KB (flash memory)
256 KB (flash memory)
8 KB
12 KB
Internal ROM Capacity
Internal RAM Capacity
x0000000H to x001FFFFH
x0000000H to x003FFFFH
xFFFC000H to xFFFDFFFH
xFFFC000H to xFFFEFFFH
Internal ROM Area
Internal RAM Area
μ
PD70F3454GC-
39