UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 620

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

618
Analog input
Registers
Control registers
A/D converters 0 and 1 consist of the following hardware.
Remark
Item
n = 0, 1
When comparator is not used: ANI00/ANI05, ANI01 to ANI04, ANI10/ANI15 to ANI12/ANI17, ANI13,
When comparator is used (when comparators of low-range and full-range are used):
When comparator is used (when comparator of low-range or full-range is used):
Successive approximation register (SAR)
A/Dn conversion result registers 0 to 15 (ADnCR0 to ADnCR15)
A/Dn conversion result registers 0H to 15H (ADnCR0H to ADnCR15H)
A/Dn conversion result extension registers 0 to 4 (ADnECR0 to ADnECR4)
A/Dn conversion result extension registers 0H to 4H (ADnECR0H to ADnECR4H)
A/D converter n scan mode register (ADnSCM)
A/D converter n scan mode register L (ADnSCML)
A/D converter n scan mode register H (ADnSCMH)
A/D converter n conversion time control register (ADnCTC)
A/D converter n conversion channel specification register (ADnCHEN)
A/D converter n conversion channel specification register L (ADnCHENL)
A/D converter n conversion channel specification register H (ADnCHENH)
A/D converter n control register (ADnCTL0)
A/D converter n trigger select register (ADnTSEL)
A/D converter n channel specification register 1 (ADnCH1)
A/D converter n channel specification register 2 (ADnCH2)
A/D converter n flag register (ADnFLG)
A/D converter n flag buffer register (ADnFLGB)
A/DLDTRG1 input select register (ADLTS1)
A/DLDTRG2 input select register (ADLTS2)
A/D converter n clock select register (ADnOCKS)
A/D trigger falling edge specification register (ADTF)
A/D trigger rising edge specification register (ADTR)
Operational amplifier n control register 0 (OPnCTL0)
Comparator n control register 0 (CMPnCTL0)
Comparator n control register 1 (CMPnCTL1)
Comparator n control register 2 (CMPnCTL2)
Comparator n control register 3 (CMPnCTL3)
Comparator output digital noise elimination register nL (CMPNFCnL)
Comparator output digital noise elimination register nF (CMPNFCnF)
Comparator output interrupt rising edge specification register (CMPOR)
Comparator output interrupt falling edge specification register (CMPOF)
(only in extension operation mode (extension buffer mode))
(only in extension operation mode (extension buffer mode))
Table 12-1. Configuration of A/D Converters 0 and 1
CHAPTER 12 A/D CONVERTERS 0 AND 1
User’s Manual U18279EJ3V0UD
ANI14 (total of 10 channels in two circuits)
ANI00/ANI05, ANI01, ANI02, ANI10/ANI15 to ANI12/ANI17
(total of 6 channels in two circuits)
ANI00/ANI05, ANI01, ANI02, ANI03 or ANI04, ANI10/ANI15 to
ANI12/ANI17, ANI13 or ANI14 (total of 8 channels in two circuits)
Configuration