UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 284

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

282
(b) Pulse width measurement with capture register
When pulse width measurement is performed with the TAAmCCRa register used as a capture register,
software processing is necessary for reading the capture register each time the INTTAmCCa signal has
been detected and for calculating an interval.
When executing pulse width measurement in the free-running timer mode, two pulse widths can be
measured with one channel.
To measure a pulse width, the pulse width can be calculated by reading the value of the TAAmCCRa
register in synchronization with the INTTAmCCa signal, and calculating the difference between the read
value and the previously read value.
Remark
TAAmCCR1 register
TAAmCCR0 register
INTTAmCC1 signal
INTTAmCC0 signal
INTTAmOV signal
TIAm0 pin input
TIAm1 pin input
16-bit counter
TAAmOVF bit
TAAmCE bit
V850E/IF3: m = 2, 4, a = 0, 1
V850E/IG3: m = 2 to 4, a = 0, 1
FFFFH
0000H
CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA)
0000H
Pulse interval
0000H
Pulse interval
(D
User’s Manual U18279EJ3V0UD
D
00
(D
)
D
00
10
10
)
Pulse interval
(10000H +
D
D
01
Cleared to 0 by
CLR instruction
Pulse interval
00
- D
(10000H +
D
D
00
11
)
01
D
− D
D
10
Pulse interval
11
10
(D
)
02
− D
D
D
Pulse interval
02
01
01
(10000H +
D
)
D
12
Cleared to 0 by
CLR instruction
11
− D
Pulse interval
(10000H +
D
D
03
11
12
)
D
− D
D
02
03
02
)
Pulse interval
(10000H +
D
13
Pulse interval
(10000H +
− D
D
D
04
D
12
D
Cleared to 0 by
CLR instruction
− D
12
03
13
)
03
)
D
04
D
D
13
04