UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 701

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UPD70F3451GC-UBT-A

Manufacturer Part Number
UPD70F3451GC-UBT-A
Description
MCU 32BIT 128KB FLASH 80LQFP
Manufacturer
Renesas Electronics America
Series
V850E/Ix3r
Datasheet

Specifications of UPD70F3451GC-UBT-A

Core Processor
RISC
Core Size
32-Bit
Speed
64MHz
Connectivity
CSI, I²C, UART/USART
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
44
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3.5 V ~ 5.5 V
Data Converters
A/D 10x12b, 4x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD70F3451GC-UBT-A
Manufacturer:
Renesas Electronics America
Quantity:
10 000
13.4.2 Trigger mode
Trigger mode that serve as the start timing of an A/D conversion operation is software trigger mode.
This mode is set by the AD2M0 register.
(1) Software trigger mode
Remark
In this mode, the analog input pin (ANI2n) specified by the AD2S.AD2S2 to AD2S.AD2S0 bits is used for the
A/D conversion start timing by setting the AD2M0.AD2CE bit to 1.
After A/D conversion ends, the conversion result is stored in A/D2 conversion result register n (AD2CRn).
An A/D2 conversion end interrupt request signal (INTAD2) is generated simultaneously when A/D conversion
operations are completed in the select mode. INTAD2 interrupt request signal is generated when all the
specified A/D conversion operations are completed in the scan mode.
If the operation mode set by the AD2M0.AD2MD1 and AD2M0.AD2MD0 bits is the continuous select mode or
continuous scan mode, the conversion operation is repeated unless the AD2M0.AD2CE bit is set to 0. In the
one-shot select mode or one-shot scan mode, the conversion operation is stopped after A/D conversion ends.
The AD2M0.AD2EF bit is set to 1 (conversion in progress) when A/D conversion is started, and set to 0
(conversion stops) when it is completed.
If the AD2M0 and AD2S registers are written during A/D conversion, the conversion is stopped and executed
again from the beginning.
V850E/IF3: n = 0 to 3
V850E/IG3: n = 0 to 7
CHAPTER 13 A/D CONVERTER 2
User’s Manual U18279EJ3V0UD
699

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