UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 879

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

17.6.4 ACK
receiving device, the reception is judged as normal and processing continues. The detection of ACK is confirmed with
the IICS0.ACKD0 bit.
the stop condition. When the slave device is the receiving device and does not return ACK, the master device
generates either a stop condition or a restart condition, and then stops the current transmission. Failure to return ACK
may be caused by the following factors.
reception).
following the 7 address data bits causes the IICS0.TRC0 bit to be set. Normally, set the ACKE0 bit to 1 for reception
(TRC0 bit = 0).
receive any more data, clear the ACKE0 bit to 0 to indicate to the master that no more data can be received.
the ACKE0 bit to 0 to prevent ACK from being generated. This notifies the slave device (transmitting device) of the
end of the data transmission (transmission stopped).
ACK is generated if the received address is not a local address (NACK).
ACK is used to confirm the serial data status of the transmitting and receiving devices.
The receiving device returns ACK for every 8 bits of data it receives.
The transmitting device normally receives ACK after transmitting 8 bits of data. When ACK is returned from the
When the master device is the receiving device, after receiving the final data, it does not return ACK and generates
(a) Reception was not performed normally.
(b) The final data was received.
(c) The receiving device (slave) does not exist for the specified address.
When the receiving device sets the SDA line to low level during the ninth clock, ACK is generated (normal
When the IICC0.ACKE0 bit is set to 1, automatic ACK generation is enabled. Transmission of the eighth bit
When the slave device is receiving (when TRC0 bit = 0), if the slave device cannot receive data or does not need to
Similarly, when the master device is receiving (when TRC0 bit = 0) and the subsequent data is not needed, clear
When the local address is received, ACK is automatically generated regardless of the value of the ACKE0 bit. No
When receiving the extension code, set the ACKE0 bit to 1 in advance to generate ACK.
The ACK generation method during data reception is based on the wait timing setting, as described by the following.
• When 8-clock wait is selected (IICC0.WTIM0 bit = 0):
• When 9-clock wait is selected (IICC0.WTIM0 bit = 1):
ACK is generated at the falling edge of the SCL pin’s eighth clock if the ACKE0 bit is set to 1 before the wait
state cancellation.
ACK is generated if the ACKE0 bit is set to 1 in advance.
SDA
SCL
AD6
1
AD5
2
User’s Manual U18279EJ3V0UD
CHAPTER 17 I
Figure 17-9. ACK
AD4
3
AD3
4
2
AD2
C BUS
5
AD1
6
AD0
7
R/W ACK
8
9
877