UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 187

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

5.5
5.5.1
5.5.2
in the
it is in the stopped status (×), the pin cannot output the clock.
Normal operation
HALT mode
IDLE mode
In STOP mode and during oscillation
stabilization time count after release of STOP
mode
During RESET pin input
oscillation stabilization time count
The following table shows the operation status of each clock.
Notes 1.
Remark √: Operating
The clock output function is used to output the external bus clock (f
When the internal system clock (f
μ
Operation
PD70F3454GC-8EA-A and 70F3454F1-DA9-A.
Operation of each clock
Clock output function
2. The peripheral clock (f
3. Operation continues during on-chip debugging.
4. RESET pin input, reset signal (WDTRES) generation by watchdog timer, reset signal (LVIRES)
5. The output from the prescaler (PRS) in not performed.
6. The clock is not output from the CLKOUT pin.
×: Stopped
Power Save Mode
μ
generation by low-voltage detector (LVI), or reset signal (POCRES) generation by power-on-clear
circuit (POC)
PD70F3454GC-8EA-A and 70F3454F1-DA9-A only
Note 4
and subsequent
Table 5-2. Operation Status of Each Clock
CLK
XX
/1024) is used as the watchdog timer clock.
) in Table 5-2 is in the operable status (√), the pin can output the clock. When
CHAPTER 5 CLOCK GENERATOR
Oscillator
User’s Manual U18279EJ3V0UD
×
(f
Note 3
√
√
√
√
X
)
× → √
×
PLL
Note 3
√
√
√
Internal
System
Clock
(f
CLK
√
√
×
×
√
BUS
)
) from the CLKOUT pin and supported only
Peripheral
f
XX
Clock
(f
×
/4096)
XX
Note 5
√
√
×
×
to
Bus Clock
(f
External
BUS
×
Note 6
√
√
×
×
)
Note 1
Clock
(f
CPU
CPU
√
×
×
×
√
)
Watchdog
Clock
Timer
√
√
×
×
×
Note 2
185