UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 916

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

17.16.1 Master operation in single master system
914
Note Release the I
Remark For the transmission and reception formats, conform to the specifications of the product in
communication. For example, when the EEPROM
to the output port and output clock pulses from that output port until when the SDA pin is constantly high
level.
communication.
2
C bus (SCL, SDA pins = high level) in conformity with the specifications of the product in
No
No
Figure 17-16. Master Operation in Single Master System
ACKE0 = WTIM0 = SPIE0 = 1
Set STCEN0, IICRSV0 = 0
Initialize I
interrupt occurred?
interrupt occurred?
interrupt occurred?
Transfer ended?
IICCL0 ← XXH
SVA0 ← XXH
IICC0 ← XXH
STCEN0 = 1?
IICX0 ← 0XH
IICF0 ← 0XH
ACKD0 = 1?
ACKD0 = 1?
Restarted?
TRC0 = 1?
Write IIC0
Write IIC0
Set ports
IICE0 = 1
SPT0 = 1
STT0 = 1
START
INTIIC
INTIIC
INTIIC
2
C bus
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Note
Waiting for stop condition detection
Yes
No
No
No
No
No
No
User’s Manual U18279EJ3V0UD
Communication start preparation
(stop condition generation)
See Table 4-14 Settings When Port Pins Are Used for Alternate Functions
to set the I
Transfer clock selection
Local address setting
Start condition setting
Communication start preparation
(start condition generation)
Communication start
(address, transfer direction specification)
Waiting for ACK detection
Transmission start
Waiting for data transmission
CHAPTER 17 I
SPT0 = 1
2
END
C mode before this function is used.
TM
2
outputs a low level to the SDA pin, set the SCL pin
C BUS
WTIM0 = WREL0 = 1
interrupt occurred?
interrupt occurred?
Transfer ended?
WREL0 = 1
ACKE0 = 1
ACKE0 = 0
WTIM0 = 0
Read IIC0
INTIIC
INTIIC
Yes
Yes
Yes
No
No
No
Reception start
Waiting for
data reception
Waiting for ACK detection