UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 16

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

CHAPTER 16 CLOCKED SERIAL INTERFACE B (CSIB)............................................................... 806
CHAPTER 17 I
14
15.9 Control Flow ........................................................................................................................... 793
15.10 Cautions .................................................................................................................................. 804
16.1 Mode Switching Between CSIB and Other Serial Interface ............................................... 806
16.2 Features .................................................................................................................................. 809
16.3 Configuration.......................................................................................................................... 810
16.4 Control Registers ................................................................................................................... 812
16.5 Operation ................................................................................................................................ 819
16.6 Output Pins ............................................................................................................................. 852
17.1 Mode Switching Between I
17.2 Features .................................................................................................................................. 854
17.3 Configuration.......................................................................................................................... 857
17.4 Registers ................................................................................................................................. 859
17.5 Functions ................................................................................................................................ 873
17.6 I
17.7 I
16.1.1
16.1.2
16.1.3
16.5.1
16.5.2
16.5.3
16.5.4
16.5.5
16.5.6
16.5.7
16.5.8
16.5.9
16.5.10 Continuous transfer mode (slave mode, transmission mode) ....................................................840
16.5.11 Continuous transfer mode (slave mode, reception mode) .........................................................842
16.5.12 Continuous transfer mode (slave mode, transmission/reception mode) ....................................845
16.5.13 Reception error..........................................................................................................................849
16.5.14 Clock timing ...............................................................................................................................850
17.5.1
17.6.1
17.6.2
17.6.3
17.6.4
17.6.5
17.6.6
17.6.7
17.7.1
17.7.2
17.7.3
2
2
C Bus Definitions and Control Methods ............................................................................ 874
C Interrupt Request Signals (INTIIC).................................................................................. 882
2
C BUS .......................................................................................................................... 853
Mode switching between CSIB0 and UARTA0 ..........................................................................806
Mode switching between CSIB1 and UARTA2 ..........................................................................807
Mode switching between CSIB2 and UARTB ............................................................................808
Single transfer mode (master mode, transmission mode) .........................................................819
Single transfer mode (master mode, reception mode)...............................................................821
Single transfer mode (master mode, transmission/reception mode)..........................................823
Single transfer mode (slave mode, transmission mode) ............................................................825
Single transfer mode (slave mode, reception mode) .................................................................827
Single transfer mode (slave mode, transmission/reception mode) ............................................829
Continuous transfer mode (master mode, transmission mode) .................................................831
Continuous transfer mode (master mode, reception mode).......................................................833
Continuous transfer mode (master mode, transmission/reception mode)..................................836
Pin configuration........................................................................................................................873
Start condition............................................................................................................................874
Addresses..................................................................................................................................875
Transfer direction specification ..................................................................................................876
ACK ...........................................................................................................................................877
Stop condition............................................................................................................................878
Wait state ..................................................................................................................................879
Wait state cancellation method..................................................................................................881
Master device operation ............................................................................................................883
Slave device operation (when receiving slave address data (address match))..........................886
Slave device operation (when receiving extension code) ..........................................................890
2
C and UARTA1 ......................................................................... 853
User’s Manual U18279EJ3V0UD