UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 251

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

<1> Count operation start flow
<2> TAAmCCR0 and TAAmCCR1 register
(TAAmCKS0 to TAAmCKS2 bits)
Setting of TAAmCCR0 register
Setting of TAAmCCR1 register
setting change flow
Remark
TAAmCCR0 register,
Register initial setting
TAAmCTL1 register,
TAAmIOC0 register,
TAAmIOC2 register,
TAAmCCR1 register
TAAmCTL0 register
TAAmCE bit = 1
Figure 6-27. Software Processing Flow in External Trigger Pulse Output Mode (2/2)
START
V850E/IF3: m = 2, 4, a = 0, 1
V850E/IG3: m = 2 to 4, a = 0, 1
CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA)
Initial setting of these
registers is performed
before setting the
TAAmCE bit to 1.
The TAAmCKS0 to
TAAmCKS2 bits can be
set at the same time when
counting is enabled
(TAAmCE bit = 1).
Trigger wait status.
Writing same value
(same as preset value of
the TAAmCCR1 register)
to the TAAmCCR1
register is necessary only
when the set cycle is changed.
When the counter is
cleared after setting,
the value of the TAAmCCRa
register is transferred to
the CCRa buffer register.
User’s Manual U18279EJ3V0UD
<3> TAAmCCR0, TAAmCCR1 register
<4> TAAmCCR0, TAAmCCR1 register
<5> Count operation stop flow
Setting of TAAmCCR1 register
Setting of TAAmCCR0 register
Setting of TAAmCCR1 register
setting change flow
setting change flow
TAAmCE bit = 0
STOP
Counting is stopped.
Only writing of the TAAmCCR1
register must be performed when
only the set duty factor is changed.
When the counter is cleared after
setting, the value of the
TAAmCCRa register is transferred
to the CCRa buffer register.
When the counter is
cleared after setting,
the value of the TAAmCCRa
register is transferred to
the CCRa buffer register.
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