UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 975

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

19.4 Transfer Modes
19.4.1 Single transfer mode
transfer request, transfer is performed again once. This operation continues until a terminal count occurs.
DMA request always takes precedence. If another DMA transfer request with a lower priority occurs one clock after
single transfer has been completed, however, this request does not take precedence even if the previous DMA
transfer request signal with a higher priority remains active. DMA transfer with the newly requested lower priority
request is executed after the CPU bus has been released.
0 to 2 are in the block transfer mode and channel 3 is in the single transfer mode.
In single transfer mode, the DMAC releases the bus at each byte/halfword transfer. If there is a subsequent DMA
When the DMAC has released the bus, if another higher priority DMA transfer request is issued, the higher priority
Figures 19-1 to 19-4 show examples of single transfer.
Figure 19-2 shows an example of a single transfer in which a higher priority DMA request is issued. DMA channels
Note The bus is always released.
Note The bus is always released.
(internal signal)
(internal signal)
(internal signal)
(internal signal)
(internal signal)
DMARQ3
DMARQ0
DMARQ1
DMARQ2
DMARQ3
CPU
CPU CPU CPU DMA3 CPU DMA0 DMA0 CPU DMA1 DMA1 CPU DMA2 DMA2 CPU DMA3 CPU DMA3
CPU DMA3 CPU DMA3 CPU DMA3 CPU CPU CPU CPU CPU CPU DMA3 CPU DMA3 CPU CPU CPU
CHAPTER 19 DMA FUNCTIONS (DMA CONTROLLER)
Note
Figure 19-1. Single Transfer Example 1
Figure 19-2. Single Transfer Example 2
Note
User’s Manual U18279EJ3V0UD
Note
DMA channel 0
terminal count
Note
Note
DMA channel 1
terminal count
Note
DMA channel 2
terminal count
Note
Note
DMA channel 3
terminal count
DMA channel 3
terminal count
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