UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 304

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

302
(6) TABn option register 0 (TABnOPT0)
The TABnOPT0 register is an 8-bit register used to set the capture/compare operation and detect an overflow.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
Note For details of the TABnCMS and TABnCUF bits, see CHAPTER 10
Cautions 1. Rewrite the TABnCCS3 to TABnCCS0 bits when the TABnCE bit = 0. (The same value
FUNCTION.
TABnOPT0
a = 0 to 3
n = 0, 1
2. Be sure to set bit 3 to “0”.
After reset: 00H
can be written when the TABnCE bit = 1.) If rewriting was mistakenly performed, clear
the TABnCE bit to 0 and then set the bits again.
TABnCCSa
TABnCCS3
Set (1)
Reset (0)
The TABnCCSa bit setting is valid only in the free-running timer mode.
• The TABnOVF bit is set to 1 when the 16-bit counter count value overflows from
• An overflow interrupt request signal (INTTBnOV) is generated at the same time
• The TABnOVF bit is not cleared to 0 even when the TABnOVF bit or the
• Before clearing the TABnOVF bit to 0 after generation of the INTTBnOV signal, be
• The TABnOVF bit can be both read and written, but the TABnOVF bit cannot be
FFFFH to 0000H in the free-running timer mode or the pulse width measurement
mode.
that theTABnOVF bit is set to 1. The INTTBnOV signal is not generated in modes
other than the free-running timer mode and the pulse width measurement mode.
TABnOPT0 register are read when the TABnOVF bit = 1.
sure to confirm (by reading) that the TABnOVF bit is set to 1.
set to 1 by software. Writing 1 has no influence on the operation of TABn.
<7>
CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB)
0
1
TABnOVF
TABnCCS2 TABnCCS1 TABnCCS0
R/W
Compare register selected
Capture register selected (cleared by TABnCTL0.TABnCE bit = 0)
<6>
Address: TAB0OPT0 FFFFF5E5H, TAB1OPT0 FFFFF625H
User’s Manual U18279EJ3V0UD
Overflow occurred
TABnOVF bit 0 written or TABnCTL0.TABnCE bit = 0
TABnCCRa register capture/compare selection
<5>
<4>
TABn overflow flag
3
0
TABnCMS
<2>
Note
TABnCUF
<1>
Note
MOTOR CONTROL
TABnOVF
<0>