UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 409

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(1) 16-bit counter
(2) CCR0 buffer register
(3) CCR1 buffer register
(4) Edge detector
(5) Output controller
(6) Selector
(7) Counter control
This 16-bit counter can count internal clocks or external events.
The count value of this counter can be read by using the TTnCNT register.
When the TTnCTL0.TTnCE bit = 0, the value of the 16-bit counter is FFFFH. If the TTnCNT register is read at
this time, 0000H is read.
Reset sets the TTnCE bit to 0.
This is a 16-bit compare register that compares the count value of the 16-bit counter.
When the TTnCCR0 register is used as a compare register, the value written to the TTnCCR0 register is
transferred to the CCR0 buffer register. When the count value of the 16-bit counter matches the value of the
CCR0 buffer register, a compare match interrupt request signal (INTTTEQCn0) is generated.
The CCR0 buffer register cannot be read or written directly.
The CCR0 buffer register is set to 0000H after reset, and the TTnCCR0 register is set to 0000H.
This is a 16-bit compare register that compares the count value of the 16-bit counter.
When the TTnCCR1 register is used as a compare register, the value written to the TTnCCR1 register is
transferred to the CCR1 buffer register. When the count value of the 16-bit counter matches the value of the
CCR1 buffer register, a compare match interrupt request signal (INTTTEQCn1) is generated.
The CCR1 buffer register cannot be read or written directly.
The CCR1 buffer register is set to 0000H after reset, and the TTnCCR1 register is set to 0000H.
This circuit detects the valid edges input to the TIT00 (V850E/IG3 only), TIT01 (V850E/IG3 only), TIT10, TIT11,
EVTT0 (V850E/IG3 only), EVTT1, TENC00 (V850E/IG3 only), TENC01 (V850E/IG3 only), TENC10, TENC11,
TECR0 (V850E/IG3 only), and TECR1 pins. No edge, rising edge, falling edge, or both the rising and falling
edges can be selected as the valid edge by using the TTmIOC1, TTmIOC2, and TTmIOC3 registers.
This circuit controls the output of the TOT00 (V850E/IG3 only), TOT01 (V850E/IG3 only), TOT10, and TOT11
pins. The output controller is controlled by the TTmIOC0 registers.
This selector selects the count clock for the 16-bit counter. Eight types of internal clocks or an external event
can be selected as the count clock.
The count operation is controlled by the timer mode selected by the TTnCTL1 register.
CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT)
User’s Manual U18279EJ3V0UD
407