UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 692

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

690
A/D converter 2 consists of the following hardware.
Analog input
Registers
Control registers
(1) Successive approximation register (SAR)
(2) A/D conversion result register n (AD2CRn), A/D conversion result register nH (AD2CRnH)
(3) Sample & hold circuit
(4) Voltage comparator
The SAR register is a register that compares the voltage value of an analog input pin with the value of the
voltage tap of the D/A converter and holds the result, starting from the most significant bit (MSB).
If data is held in the SAR all the way to the least significant bit (LSB) (end of A/D conversion), the contents of
the SAR register are transferred in AD2CRn register.
When all the specified A/D conversion operations have ended, an A/D2 conversion end interrupt request signal
(INTAD2) is generated.
The AD2CRn register is a register that holds the A/D conversion results. The conversion result is stored in the
higher 10 bits of the AD2CRn register corresponding to the analog input. The lower 6 bits of these registers
are always 0 when read.
The higher 8 bits of the result of A/D conversion are read from the AD2CRn register.
To read the result of A/D conversion in 16-bit units, specify the AD2CRn register. To read the higher 8 bits,
specify the AD2CRnH register.
Caution The contents of the AD2CRn register may become undefined depending on the operation to
The sample & hold circuit samples the analog input signals selected by the input circuit and sends the sampled
data to the voltage comparator. This circuit holds the sampled analog input voltage during A/D conversion.
The voltage comparator compares the value that is sampled and held with the voltage generated from the
voltage tap of the D/A converter.
Item
write the AD2M0, AD2M1, and AD2S registers.
AD2CRn register after conversion and before writing the AD2M0, AD2M1, and AD2S registers.
The correct conversion result cannot be read from the AD2CRn register if any other
procedure is used.
V850E/IF3: ANI20 to ANI23 (4 channels)
V850E/IG3: ANI20 to ANI27 (8 channels)
Successive approximation register (SAR)
V850E/IF3:
A/D2 conversion result registers 0 to 3 (AD2CR0 to AD2CR3)
A/D2 conversion result registers 0H to 3H (AD2CR0H to AD2CR3H): Only the higher 8 bits can be
read V850E/IG3:
A/D2 conversion result registers 0 to 7 (AD2CR0 to AD2CR7)
A/D2 conversion result registers 0H to 7H (AD2CR0H to AD2CR7H): Only the higher 8 bits can be
read
A/D converter 2 mode registers 0, 1 (AD2M0, AD2M1)
A/D converter 2 channel specification register (AD2S)
Table 13-1. Configuration of A/D Converter 2
CHAPTER 13 A/D CONVERTER 2
User’s Manual U18279EJ3V0UD
Configuration
Read the result of conversion from the