TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 100

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

TMP92CF26A
3.6.5
Note
In case of using S/W start with HDMA, transmission start is to set to “1” DMAR register.
However DMAR register can't be used to confirm flag of transmission end. DMAR register
reset to “0” when HDMA release bus occupation once with HDMATR function. We
recommend to use HDMACBn register (counter value) to confirm flag of transmission end.
2009-06-25
92CF26A-98