TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 233

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

Internal system clock
Internal data bus
COMMAND
(5) Read/Write commands
D15-D0
SDCLK
A15-A0
using SDACR<SPRE>.
Precharge. When Auto Precharge is enabled, the SDRAM is automatically precharged
internally at every access cycle. Thus, the SDRAM is always in a “bank idle” state while it is
not being accessed. This helps reduce the power consumption of the SDRAM but at the cost of
degradation in performance as the Bank Active command is needed at every access cycle.
Precharge. In this case, the SDRAM is not precharged at every access cycle and is always in a
“bank active” state. This increases the power consumption of the SDRAM, but improves
performance as there is no need to issue the Bank Active command at every access cycle. If an
access is made to outside the SDRAM page boundaries or if the Auto Refresh command is
issued, the SDRAMC automatically issues the Precharge All command.
there is one limitation. When SDRAM is set as VRAM for LCD controller and DMA controller
is operated at the same time, always set to “1” to SDACR<SPRE>.
The Read/Write commands to be used in 1-word read/single write mode can be specified by
When SDACR<SPRE> is set to “1”, the Read/Write commands are executed with Auto
When SDACR<SPRE> is set to “0”, the Read/Write commands are executed without Auto
And this micro has LCD controller and DMA controller, in case of using below condition,
(c) Full-page read, the read data shift function enabled (SDACR<SRDS> = “1”,
<SRDSCK> = “0”)
NOP
Row Address
ACTIVE
READ
92CF26A-231
External data latch
NOP
ColumnAddress
NOP
DIN1
DIN1
CPU data read
NOP
DIN2
DIN2
NOP
TMP92CF26A
DIN3
2009-06-25
DIN3