TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 267

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

3.
Read (including ECC data read)
Reading valid data
; ***** Read valid data*****
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(1) Error bit calculation
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INT:
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If error is found, the error processing routine is performed to
ldw
ldw
ldw
ldw
ldw
ldw
ldw
Wait set up time (from Busy to Ready)
ldw
ldw
ldw
ldw
Wait set up time (20 system clocks)
ldw
ldw
Wait set up time
Interrupt routine (End of calculation for Reed-Solomon Error bit)
ldw
Methods”.
The read operation is repeated four times to read 2112 bytes.
correct the error data. For details see 3.11.4.2 “Error Correction
(ndfmcr0),5008h ; CE1 enable
(ndfmcr0),50A8h ; WE enable, CLE enable
(ndfdtr0),0000h
(ndfmcr0),50C8h ; ALE enable
(ndfdtr0),00xxh
(ndfmcr0),50A8h ; WE enable, CLE enable
(ndfdtr0),0030h
1. Flag polling
2. Interrupt
(ndfmcr0),540Dh ; ECC reset, ECC circuit enable, decode mode
xxxx,(ndfdtr0)
(ndfmcr0),550Ch ; RSECGW enable
xxxx,(ndfdtr0)
(ndfmcr1),0047h ; Error bit calculation interrupt enable
(ndfmcr0),560Ch ; Error bit calculation circuit start
xxxx,(ndfmcr1)
92CF26A-265
; Read command 1
; Address write (4 or 5 times)
; Read command 2
; Data read (259 times: 518 bytes)
; Read ECC (5 times: 80 bits)
; Check error status ”STATE3:0, SEER1:0”
(256-times:512 byte)
TMP92CF26A
2009-06-25