TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 38

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TMP92xy26AXBG

Manufacturer Part Number
TMP92xy26AXBG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMP92xy26AXBG

Package
FPGA228
Rom Types(m=mask,p=otp, F=flash,e=eeprom)
Romless
Rom Combinations
Romless
Ram Combinations
144/288
Architecture
32-bit CISC
Usb/spi Channels
1/1
Uart/sio Channels
2
I2c/sio Bus Channels
1
(s)dram Controller
1
Adc 10-bit Channel
6
Da Converter
-
Timer 8-bit Channel
8
Timer 16-bit Channel
2
Pwm 8-bit Channels
-
Pwm 16-bit Channels
-
Cs/wait Controller
4
Dual Clock
Y
Number Of I/o Ports
136
Power Supply Voltage(v)
3.0 to 3.6
Address
8200H
8203H
8206H
8209H
820BH
820EH
820FH
An INT0 interrupt clears the Halt state when the device is in IDLE1 Mode.
(Example - releasing IDLE1 Mode)
INT0
LD
LD
LD
EI
LD
HALT
LD
(PCFC), 02H
(IIMC0), 00H
(INTE0), 06H
5
(SYSCR2), 28H
XX, XX
92CF26A-36
; Sets PC1 to INT0 interrupt.
; Select INT0 interrupt rising edge.
; Sets INT0 interrupt level to 6.
; Sets CPU interrupt level to 5.
; Sets Halt mode to IDLE1 mode.
; Halts CPU.
INT0 interrupt routine.
RETI
TMP92CF26A
2009-06-25

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