TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 439

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

INT_SETUP
INT_ ENDPOINT0
INT_STATUS
REQUEST FLAG
DATASET register
BRD
BWR
SETUP DATA0 ACK
bmRequestType register
bRequest register
wValue register
wINdex register
wLength register
Figure 3.16.8 The Control Flow in UDC (Control Write Transfer Type not Dataphase)
These change condition is
Figure 3.16.8.
1.
2.
Stage change condition of control write (no data stage) transfer type
• Start setup stage in the UDC.
• Receive data in request normally and judge. And assert INT_SETUP
• Change data stage in the UDC.
• CPU receives a request from the request register every INT_SETUP
• Judge request and access Setup Received register to inform the UDC that
• The CPU processes receiving data by device request.
• When the CPU finishes transaction, it writes “0” to EP0 bit of EOP register.
• Change status stage in the UDC.
• Return data packet of 0 data to IN token, and change state to IDLE in the
• Assert INT_STATUS interrupt externally when ACK for 0 data packet is
Receive SETUP token from host
Receive IN token from host
interrupt externally.
interrupt.
INT_SETUP interrupt has been recognized.
UDC.
received.
Setup Received register
IN
NAK
92CF26A-437
IN
DATA1
EOP register
ACK
TMP92CF26A
2009-06-25