TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 583
TMP92xy26AXBG
Manufacturer Part Number
TMP92xy26AXBG
Description
Manufacturer
Toshiba
Datasheet
1.TMP92XY26AXBG.pdf
(768 pages)
Specifications of TMP92xy26AXBG
Package
FPGA228
Rom Types(m=mask,p=otp, F=flash,e=eeprom)
Romless
Rom Combinations
Romless
Ram Combinations
144/288
Architecture
32-bit CISC
Usb/spi Channels
1/1
Uart/sio Channels
2
I2c/sio Bus Channels
1
(s)dram Controller
1
Adc 10-bit Channel
6
Da Converter
-
Timer 8-bit Channel
8
Timer 16-bit Channel
2
Pwm 8-bit Channels
-
Pwm 16-bit Channels
-
Cs/wait Controller
4
Dual Clock
Y
Number Of I/o Ports
136
Power Supply Voltage(v)
3.0 to 3.6
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P96/INT4 pin
INT4
Reset the debounce time counter
The debounce time counter matches with a
specified debounce time, which generates an
INT4 interrupt.
Figure 3.20.4 Timing diagram of debounce circuit
Start the debounce time counter
Debounce time
No INT4 interrupt is generated due to edge interrupt even though
the debounce time counter matches a specified debounce time.
92CF26A-581
Debounce time
After the pen is released, an INT4 interrupt can
be received again.
Debounce time
TMP92CF26A
2009-06-25
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