TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 564

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

(7) LDIV Signal
LDIV signal as well as data output. The LDIV signal indicates the inversion of all the LD
bus signals.
signal is also driven high. When LCDMODE1<AUTOINV>=1, the data that has just been
transferred and the data to be transferred next are compared. If there are more changed
bits than unchanged bits (for example, 7 or more bits are changed when using a 12-bit bus,
and 5 or more bits are changed when using a 8-bit bus), the data is inverted and the LDIV
signal is also driven high. This function can be used with TFT source drivers having the
data inversion function to reduce radiated noise and power consumption due to high-speed
data inversion.
priority and <AUTOINV> is disabled.
The <LDINV> and <AUTOINV> bits of the LCDMODE1 register are used to control the
When LCDMODE1<LDINV>=1, all display data is forcefully inverted and the LDIV
If <LDINV> and <AUTOINV> are both set to “1” at the same time, <LDINV> is given
92CF26A-562
TMP92CF26A
2009-06-25