TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 651

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

PZDR
(009AH)
PZCR
(006AH)
PZFC
(006BH)
PZ
(0068H)
bit Symbol
Read/Write
Reset State
bit Symbol
Read/Write
Reset State
Function
bit Symbol
Read/Write
Reset State
Function
bit Symbol
Read/Write
Reset State
Function
Note: Although it is possible to write to shaded bits, writing to these bits has no effect (the DSU communication
function is given a higher priority).
2) Pins
used to connect the TMP92CF26A with an emulator via a DSU probe for
communicating with the controller. For this reason, these 9 pins cannot be
debugged. Therefore, if the port control register of each pin is changed in debug
mode, the register contents are changed but the function of each pin remains the
same.
PZ7C
PZ7D
PZ7F
PZ7
7
7
7
7
In debug mode, a total of 9 pins (PZ0 to PZ7 in Port Z and PU7 in Port U) are
0
0
1
PZ6C
PZ6F
PZ6D
PZ6
6
6
6
6
0
0
1
Input/output buffer drive register for standby mode
Port Z Function Register
External pin data (Output latch is reset to “0”.)
Port Z Control Register
PZ5C
PZ5F
PZ5D
Port Z Drive Register
PZ5
0
1
5
5
5
5
0
92CF26A-649
Port Z Register
0: Input
PZ4C
PZ4D
PZ4F
PZ4
0
4
4
0
4
4
1
0: Port
R/W
R/W
W
W
1: Output
PZ3C
PZ3D
PZ3F
PZ3
3
3
0
3
0
3
1
PZ2C
PZ2D
PZ2F
PZ2
2
2
2
2
0
0
1
PZ1C
PZ1F
PZ1D
PZ1
1
1
1
1
1
0
0
TMP92CF26A
PZ0C
PZ0D
PZ0F
PZ0
0
0
0
0
1
0
0
2009-06-25