TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 425

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

(2) Transfer mode
•
UDC supports FULL speed transfer mode.
The following is an explanation of UDC operation in each transfer mode.
The explanation is of data flow up until FIFO.
(a) Bulk transfer type
FULL speed device
using detect error and retry. Basically, 3 phases are used - token, data and handshake.
However, with flow control and a STALL condition, data phase is changed to hand
shake phase, and it become to 2 phases. The UDC holds status of each endpoint, and
flow control is controlled in hardware. Each endpoint condition can be confirmed
using EPx_STATUS register.
Control transfer type
Interrupt transfer type
Bulk transfer type
Isochronous transfer type
Bulk transfer type warrants transferring no error between host and function by
92CF26A-423
TMP92CF26A
2009-06-25