TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 177

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

3.7.24
input or output. Resetting sets ports Z0 to Z7 to input port and output latch to “0”.
communication pin for debug mode (EI_PODDATA, EI_SYNCLK, EI_PODREQ,
EI_REFCLK, EI_TRGIN, EI_COMRESET, EO_MCUDATA and EO_MCUREQ). These
functions are operated when it is started in debug mode. (There is not Function register in
this port. When DBGE is set to “0”, this port is set to debug communication function.)
Port Z (PZ0 to PZ7)
Ports Z0 to Z7 are 8-bit general-purpose I/O ports. Each bit can be set individually for
In addition to functioning as general-purpose I/O port, ports Z can also function as a
Output latch
PZ write
Reset
R
(on bit basis)
PZ read
Direction
PZCR write
control
EI_PODDATA
EI_SYNCLK
EI_PODREQ
EI_REFCLK
EI_TRGIN
EI_COMRESET
Figure 3.7.66 Port Z0 to Z5
Selector
S
A
B
92CF26A-175
Debug mode
PZ0 (EI_PODDATA)
PZ1 (EI_SYNCLK)
PZ2 (EI_PODREQ)
PZ3 (EI_REFCLK)
PZ4 (EI_TRGIN)
PZ5 (EI_COMRESET)
TMP92CF26A
2009-06-25