TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 208

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

FFFF00H
FFFFFFH
Address memory map
000000H
200000H
3FE000H
400000H
600000H
800000H
C00000H
On-chip I/O, RAM
COMMON-Z
COMMON-X
COMMON-Y
Vector area
LOCAL-Z
LOCAL-X
LOCAL-Y
Note: In case of connecting SDRAM to the Z-area, the maximum expanded memory size is 64 MB (4 MB × 16).
Note: In case of connecting SDRAM to the Z-area, the maximum expanded memory size is 64 MB (4 MB × 16) .
Figure 3.9.4 Recommended Memory Map for a Simple System (Physical address)
(4 MB)
(4 MB)
Figure 3.9.3 Recommended Memory Map for a Simple System (Logical address)
(2 MB)
(2 MB)
(2 MB)
(2 MB)
Bank 0
On-chip boot ROM (8 KB)
On-chip boot ROM
On-chip I/O
and RAM
:
:
On-chip memory area
Memory area overlapping with COMMON-area, which cannot be configured as LOCAL-area.
3FE000H
000000H
1
SDCS
2
64 MB (4 MB × 16)
3
pin
92CF26A
92CF26A-206
・・・ 15
ND
ND
1
0
CE
CE
pin (512 MB)
pin (512 MB)
4 MB ×16 = 64 MB
SDCS
LOCAL-Z
SDCS (Note)
Bank 15
Bank 0
Memory controller
setting
CS2-space
TMP92CF26A
8 MB
2009-06-25