TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 534

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

LCDHSP
(028AH)
(028BH)
3.19.3.6 Refresh Rate
bit Symbol
Read/Write
Reset State
Function
bit Symbol
Read/Write
Reset State
Function
TFT
STN
product of the value set in LCDHSP<LH15:0> and the LCP0 clock period.
Segment size + number of dummy clocks
Monochrome/grayscale
Color
LHSYNC [s: period] = LCP0 [s: period] × (<LH15:0> + 1)
The period of the horizontal synchronization signal LHSYNC is defined as the
The value to be set in LCDHSP<LH15:0> is obtained as follows:
LH15
LH7
7
0
7
0
LH14
LH6
6
6
0
0
LCD LHSYNC Pulse Register
92CF26A-532
LH13
: (Segment size / 8) + number of dummy clocks
: (Segment size × 3 / 8) + number of dummy clocks
LH5
5
5
0
0
LHSYNC period (bits 7–0)
LHSYNC period (bits 15-8)
LH12
LH4
4
0
4
0
W
W
(*)
LH11
LH3
3
3
0
0
LH10
LH2
2
2
0
0
LH1
LH9
1
0
1
0
TMP92CF26A
2009-06-25
(*)
LH0
LH8
0
0
0
0
(*)