TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 611

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

ADMOD0
(12B8H)
3.23.1
bit Symbol
Read/Write
Reset State
Function
ADMOD2, ADMOD3, ADMOD4 and ADMOD5). AD conversion results are stored in the six
registers of AD conversion result higher-order/lower-order registers ADREG0H/L to
ADREG5H/L. Top-priority conversion results are stored in ADREGSPH/L.
Control register
The AD converter is controlled by the AD mode control registers (ADMOD0, ADMOD1,
Figure 3.23.2 to Figure 3.23.11 show the registers available in the AD converter.
0:During
1:Complete
Normal AD
conversion
end flag
conversion
sequence
or before
starting
conversion
sequence
AD Mode Control Register 0 (Normal conversion control)
EOS
7
0
R
Figure 3.23.2 AD Conversion Registers
0:Stop
1:During
Normal AD
conversion
BUSY Flag
conversion
conversion
BUSY
6
0
92CF26A-609
5
AD
conversion
when
IDLE2
mode
0: Stop
1: Operate
I2AD
4
0
0: Don’t Care
1:Start AD
Start Normal
AD
conversion
Always read
as”0”.
conversion
ADS
3
0
Normal AD
conversion
at Hard
ware trigger
0: Disable
1: Enable
HTRGE
R/W
2
0
Select Hard ware trigger
00: INTTB00 interrupt
01: Reserved
10:
11: Reserved
TSEL1
ADTRG
1
0
TMP92CF26A
2009-06-25
TSEL0
0
0