TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 361

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

SCL pin
SDA pin
<PIN>
INTSBI
interrupt request
Output of master
Output of slave
Figure 3.15.14 Start condition generation and slave address transfer
Start condition
After the start condition is received from the master device, while eight clocks are
output from the SCL pin, the slave address and the direction bit that are output
from the master device are received.
When a GENERAL CALL or the same address as the slave address set in I2CAR
is received, the SDA line is pulled down to the Low-level at the 9th clock, and the
acknowledge signal is output.
An INTSBI interrupt request occurs on the falling edge of the 9th clock. The
<PIN> is cleared to “0”. In Slave Mode the SCL line is pulled down to the
Low-level while the <PIN> = “0”.
b.
In the Slave Mode, the start condition and the slave address are received.
A6
1
Slave Mode
A5
2
A4
3
Slave address + Direction bit
92CF26A-359
A3
4
A2
5
A1
6
A0
7
R/
8
W
ACK
TMP92CF26A
9
Acknowledge
signal from a
slave device
2009-06-25