TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 173

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

PWFC
(00AFH)
PW
(00ACH)
PWCR
(00AEH)
PWDR
(009EH)
bit Symbol
Read/Write
System
Reset State
Hot Reset
State
bit Symbol
Read/Write
System
Reset State
Hot Reset
State
Function
bit Symbol
Read/Write
System
Reset State
Hot Reset
State
Function
bit Symbol
Read/Write
System
Reset State
Hot Reset
State
Function
Note1: A read-modify-write operation cannot be performed for the registers PWCR, PWFC.
PW7C
PW7D
PW7F
PW7
7
7
7
7
1
−
0
−
0
−
PW6C
PW6D
PW6F
PW6
Figure 3.7.62 Register for Port W
6
6
6
0
−
6
1
−
0
−
Data from external port (Output latch register is cleared to “0”)
Input/Output buffer drive register for standby mode
Port W function register
Port W control register
PW5C
PW5F
PW5D
PW5
Port W drive register
5
5
5
0
−
5
1
−
0
−
92CF26A-171
Port W register
0: Port 1: Reserved
PW4C
PW4F
PW4D
PW4
0: Input 1: Output
4
4
4
4
1
−
0
−
0
−
R/W
R/W
W
W
−
PW3C
PW3D
PW3F
PW3
3
3
3
3
0
−
0
−
1
−
PW2C
PW2F
PW2D
PW2
2
2
2
2
0
−
0
−
1
−
PW1D
PW1C
PW1F
PW1
1
1
1
1
0
−
0
−
1
−
TMP92CF26A
PW0D
PW0C
PW0F
PW0
0
0
0
0
0
0
−
−
1
−
2009-06-25