TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 329

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

Note: Overrun errors are generated only with regard to receive buffer 2 (SC0BUF). Thus, if SC0CR<RB8> is not read,
(10) Transmission buffer
(12) Error flags
(11) Parity control circuit
no overrun error will occur.
written from the CPU in order from the least significant bit (LSB). When all the bits
are shifted out, the transmission buffer becomes empty and generates an INTTX0
interrupt.
transmit and receive data with parity. However, parity can be added only in 7-bit
UART mode or 8-bit UART mode. The SC0CR<EVEN> field in the serial channel
control register allows either even or odd parity to be selected.
to the transmission buffer SC0BUF. The data is transmitted after the parity bit has
been stored in SC0BUF<TB7> in 7-bit UART mode or in SC0MOD0<TB8> in 8-bit
UART mode. SC0CR<PE> and SC0CR<EVEN> must be set before the transmission
data is written to the transmission buffer.
after the data has been transferred to receiving buffer 2 (SC0BUF), and then compared
with SC0BUF<RB7> in 7-bit UART mode or with SC0CR<RB8> in 8-bit UART mode.
If they are not equal, a parity error is generated and the SC0CR<PERR> flag is set.
1.
The transmission buffer (SC0BUF) shifts out and sends the transmission data
When SC0CR<PE> in the serial channel control register is set to 1, it is possible to
In the case of transmission, parity is automatically generated when data is written
In the case of receiving, data is shifted into receiving buffer 1, and the parity is added
Three error flags are provided to increase the reliability of data reception.
valid data still remains stored in receiving buffer 2 (SC0BUF), an overrun error is
generated.
Overrun error <OERR>
If all the bits of the next data item have been received in receiving buffer 1 while
The below is a recommended flow when the overrun error is generated.
(INTRX interrupt routine)
1) Read receiving buffer
2) Read error flag
3) If <OERR> = 1
4) Others
then
a) Set to disable receiving (Write 0 to SC0MOD0<RXE>)
b) Wait to terminate current frame
c) Read receiving buffer
d) Read error flag
e) Set to enable receiving (Write 1 to SC0MOD0<RXE>)
f) Request to transmit again
92CF26A-327
TMP92CF26A
2009-06-25