TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 107

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

LHSYNC
LCP0
LD-bus
LDMA1
HDMA
(Worst case)
LDMA2
(4) CPU + LDMA+ ARDMA + HDMA
LHSYNC [period: s] − LCD driver data transfer time [s] − t
In the case of STN display
In the case of TFT display
perform LDMA properly, the priorities among the four bus masters should be set in the
order of LDMA > ARDMA > HDMA > CPU.
shall be considered first.
transferring data from the LCD controller to the LCD driver, and the transfer
operation (LDMA1) for reading data from the display RAM into the FIFO buffer in the
LCD controller.
HDMA is started immediately before LDMA1 is started, LDMA must wait until HDMA
has finished before it can be started (LDMA2). LDMA2 must finish operation before the
LCD driver output for the next stage is started.
This is a case in which all the bus masters are active at the same time.
Since the LCD display function cannot work properly if the LCD controller cannot
Before calculating the CPU bus stop rate, the conditions for proper LCD display
The above diagram shows the LHSYNC signal, LCP0 signal, and LD-bus signal for
LDMA is started immediately after data has been transferred to the LCD driver. If
= HDMA continuous time [s] + CPU operation time [s]
LCD driver data transfer time [s] = SegNum/8×(1/fSYS) × (LD bus transfer speed)
LCD driver data transfer time [s] = SegNum×(1/ fSYS) × (LD bus transfer speed)
92CF26A-105
Setup time 1
STOP
(LCD) [s]
TMP92CF26A
2009-06-25
Setup time 2