TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 627

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

Table 3.23.2 Correspondence between analog input channels and AD conversion result registers
3.23.2.8 Storing and Read of AD Conversion Results
3.23.2.9 Data Polling
Note: In order to detect overruns without omission, read the conversion result storage register's higher-order bits first,
Analog input channel
and than read the lower-order bits next. As this result, receiving the result of OVRn = "0" and ADRnRF = "1" for
overruns existing in the lower-order bits means that a correct conversion result has been obtained.
higher-order/lower-order registers (ADREG0H/L∼ ADRG5H/L) for the normal AD
conversion (ADREG0H/L to ADREG5H/L are read-only registers)
ADREG0H/L to ADREG3H/L one after another. In other modes, the conversion results
of channels AN0, AN1, AN2, AN3, AN4, and AN5 are each stored into ADREG0H/L,
ADREG1H/L, ADREG2H/L, ADREG3H/L, ADREG4H/L, and ADREG5H/L.
conversion result registers.
perform a polling on ADMOD0<EOS>. After confirming that ADMOD0<EOS> is set to
“1,” read the AD conversion storage register.
AD
In the channel-fix repeat conversion mode, AD conversion results are stored into
Table 3.23.2 shows the correspondence between analog input channels and AD
To process AD conversion results by using data polling without using interrupts,
(Port G)
AN0
AN1
AN2
AN3
AN4
AN5
conversion
modes than shown in
results
Other conversion
92CF26A-625
ADREG0H/L
ADREG1H/L
ADREG2H/L
ADREG3H/L
ADREG4H/L
ADREG5H/L
the right
AD Conversion result registers
are
stored
Channel-fix repeat
conversion mode
in
(per 4 times)
ADREG0H/L
ADREG1H/L
ADREG2H/L
ADREG3H/L
the
AD
conversion
TMP92CF26A
2009-06-25
result