TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 762

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

Symbol
I2S0CTL
I2S1CTL
I2S0C
I2S1C
(22) I
2
I
Control
Register0
I
Divider
Value
Setting
Register
I
Control
Register1
I
Divider
Value
Setting
Register
2
2
2
2
S (2/2)
S
S0
S
S1
Name
Address
1808H
1809H
180AH
180BH
1818H
1819H
181AH
181BH
Transmit
0: Stop
1: Start
Source
clock
0: f
1: f
Transmit
0: Stop
1: Start
Source
clock
0: f
1: f
CLKS0
CLKS1
TXE0
CK07
TXE1
CK17
R/W
SYS
PLL
SYS
PLL
R/W
R/W
R/W
7
0
0
0
0
0
0
Counter
control
0: Clear
1: Start
Counter
control
0: Clear
1: Start
*CNTE0
*CNTE1
CK06
CK16
R/W
R/W
6
0
0
0
0
92CF26A-760
Set divide frequency for CK signal (8-bit counter)
WS05
WS15
CK05
CK15
Divider value for CK signal (8-bit counter)
5
0
0
0
0
Set divided frequency for WS signal (6-bit counter)
Transmissi
-on start
BIT
0:MSB
1:LSB
Stereo
/monaural
0: Stereo
1:Monaural
Transmission
start BIT
0:MSB
1:LSB
Stereo
/monaural
0: Stereo
1:Monaural
FSEL0
FSEL1
WS04
WS14
CK04
Divider value for WS signal (6-bit counter)
CK14
DIR0
DIR1
R/W
R/W
R/W
R/W
4
0
0
0
0
0
0
0
0
R/W
R/W
Bit length
0: 8 bits
1:16 bits
Condition of
transmission
FIFO
0: data
1: None
data
Bit length
0: 8 bits
1:16 bits
Condition of
transmission
FIFO
0: data
1: None
data
TEMP0
TEMP1
WS03
WS13
CK03
CK13
BIT0
BIT1
R/W
R/W
3
R
R
0
1
0
0
0
1
0
0
R/W
R/W
Output format
00: I
10: Right
01: Left
11:Reserved
WS level
0:low left
1:high left
Output format
00: I
10: Right
01: Left
11:Reserved
WS level
0:low left
1:high left
DTFMT01 DTFMT00 SYSCKE0
DTFMT11 DTFMT10 SYSCKE1
WLVL0
WLVL1
WS02
WS12
CK02
CK12
R/W
R/W
R/W
R/W
2
2
2
0
0
0
0
0
0
0
0
S
S
Clock edge
for data
output
0:Falling
1:Rising
Clock edge
for data
output
0:Falling
1:Rising
EDGE0
EDGE1
WS01
WS11
CK01
CK11
R/W
R/W
R/W
R/W
TMP92CF26A
1
0
0
0
0
0
0
0
0
2009-06-25
System
clock
0:Disable
1:Enable
Clock enable
(After trans-
mission)
0:Operate
1:Stop
System
clock
0:Disable
1:Enable
Clock enable
(After trans-
mission)
0:Operate
1:Stop
CLKE0
CLKE1
WS00
WS10
CK00
CK10
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0