TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 501

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

3.17.3
1) Transmission
2) Reception
3) CRC
buffer being full. Also, since the FIFO write pointer does not point to the correct write position,
interrupts and transmissions are not properly executed. Therefore, the number of writes
should be controlled by using software.
performed in 16-byte units. Otherwise, the TEMP interrupt is not properly generated.
Also, since the FIFO read pointer does not point to the correct read position, interrupts and
receptions are not properly executed. Therefore, the number of reads should be controlled by
using software.
in 16–byte units. Otherwise, the RFUL interrupt is not properly generated.
to the section on the SPICRC register fro more details.) The timing of the CRC comparison
should be fully considered when performing Sequential-mode transmit and receive operation
using the FIFOs.
Note: For data transmission in units of other than 16 bytes, UNIT mode must be selected.
Note: For data reception in units of other than 16 bytes, UNIT mode must be selected.
Note: The steps 2 to 4 of the above sequence can be used DMAC. However, to perform the CRC comparison, the
The transmit FIFO buffer is overwritten if the new data is written with the transmit FIFO
In the Sequential-mode transmission, the data writes to the transmit FIFO must be
If a read operation is performed when the receive FIFO is empty, undefined data is read.
In the Sequential-mode reception, the data reads from the receive FIFO must be performed
The CRC is generated upon transmission and reception to/from the SPI slave device. (Refer
Notes on the Operations Using the FIFO Buffers
Example: Sequential-mode reception
Things to be noted when using the SPIC are as follows:
receive operation must be stopped once as described in step 3. Otherwise, the CRC1 value obtained from the
internal CRC generator unintentionally contains CRC2 as well as the valid data, which leads to an incorrect
CRC comparison.
1. Start Sequential-mode reception
2. finish valid data receive (FIFO_Full)
3. Stop data reception
4. Read valid data from the FIFO to a temporary buffer (internal RAM, etc.)
5. Read CRC1 from the CRC generator in the SPIC
6. Start CRC2 reception (upon UNIT-mode reception from the SD-CARD)
7. Compare CRC1 and CRC2
92CF26A-499
TMP92CF26A
2009-06-25