TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 307

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

A read-
modify-write
operation
cannot be
performed
TB0MOD
(1182H)
Bit symbol
Read/Write
Reset State
Function
TMRB0 source clock
Control clearing for up counter (UC10)
Capture/interrupt timing
Software capture
Always write “0”.
<TB0CPM1:0>
<TB0CLK1:0>
<TB0CP0I>
<TB0CLE>
7
−
0
R/W
6
−
0
Figure 3.13.4 Register for TMRB
00
01
10
11
00
01
10
11
TMRB0 Mode Register
0
1
0
1
Software
capture
control
0: Software
capture
1:Undefined
TB0CP0I
92CF26A-305
W*
5
1
TB0IN0 pin input
φT1
φT4
φT16
Disable
Enable clearing by match with TB0RG1H/L
Disable
Capture to TB0CP0H/L at rising edge of TB0IN0
Capture to TB0CP0H/L at rising edge of TB0IN0
Capture to TB0CP1H/L at falling edge of TB0IN0
Capture to TB0CP0H/L at rising edge of TA1OUT
Capture to TB0CP1H/L at falling edge of TA1OUT
The value of up counter is captured to TB0CP0H/L
Undefined
Capture timing
00:Disable
01:TB0IN0 ↑
10: TB0IN0 ↑ TB0IN0 ↓
11: TA1OUT ↑
TB0CPM1 TB0CPM0
INT6 occurs at
rising edge
INT6 occurs at
rising edge
INT6 occurs at
falling edge
TA1OUT ↓
INT6 occurs at rising
edge
4
0
Capture control
3
0
Control
Up counter
0:Disable
1:Enable
TB0CLE
R/W
2
0
TMRB0 source clock
00: TB0IN0 input
01: φT1
10: φT4
11: φT16
TB0CLK1
INT6 occurs at the rising
edge of TB0IN0
INT6 occurs at the rising
edge of TB0IN0
INT6 occurs at the rising
edge of TB0IN0
1
0
INT6 control
TMP92CF26A
TB0CLK0
2009-06-25
0
0