TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 451

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

Note: NULL packet can also be set by accessing EOP register.
Example:
(2) Interrupt control
DATASET_A
DATASET_B
EPx_EOPB
Interrupt signal is prepared. This function use adept system.
For detail refer to 3.16.2 900/H1 CPU I/F.
(c) Issuance of NULL packet
0 length is set to FIFO, and NULL packet can be transferred to IN token.
L level condition (where FIFO is empty). If it answer to receiving IN token by
using NULL packet in a certain period, it is answered by keeping EPx_EOPB
signal to L level.
showing space of data. Therefore, data condition (whether either has data or not)
cannot be confirmed externally.
If transmitting NULL packet, by input L pulse from EPx_EOPB signal, data of
But if NULL data is set to FIFO, it is valid only in the case whole SET signal is
However, if mode is dual packet mode, EPx_DATASET signal assert L level for
NULL
A
Neglect
92CF26A-449
NULL
completion of
NULL packet
B
transmitting
NULL
A
NULL
B
NULL
A
TMP92CF26A
2009-06-25