TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 714

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TMP92xy26AXBG

Manufacturer Part Number
TMP92xy26AXBG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMP92xy26AXBG

Package
FPGA228
Rom Types(m=mask,p=otp, F=flash,e=eeprom)
Romless
Rom Combinations
Romless
Ram Combinations
144/288
Architecture
32-bit CISC
Usb/spi Channels
1/1
Uart/sio Channels
2
I2c/sio Bus Channels
1
(s)dram Controller
1
Adc 10-bit Channel
6
Da Converter
-
Timer 8-bit Channel
8
Timer 16-bit Channel
2
Pwm 8-bit Channels
-
Pwm 16-bit Channels
-
Cs/wait Controller
4
Dual Clock
Y
Number Of I/o Ports
136
Power Supply Voltage(v)
3.0 to 3.6
Symbol
TSICR0
TSICR1
(4) TSI
TSI
control
register0
TSI
control
register1
Name
Address
01F0H
01F1H
0: Disable
1: Enable
0: Disable
1: Enable
DBC7
TSI7
R/W
7
0
0
Input gate
control of
Port
96,97
0: Enable
1: Disable
DB1024
INGE
1024
R/W
6
0
0
92CF26A-712
“N” is the number of bits between bit6 and bit0 which are set to “1”.
Detection
condition
0: no
touch
1: touch
DB256
PTST
Debounce time is set by the formula “(N*64-16) / f
256
5
R
0
0
INT4
interrupt
control
0: Disable
1: Enable
TWIEN
DB64
R/W
64
4
0
0
R/W
SPY
0 : OFF
1 : ON
PYEN
DB8
R/W
3
0
0
8
SPX
0 : OFF
1 : ON
PXEN
R/W
DB4
2
0
0
4
SMY
0 : OFF
1 : ON
MYEN
R/W
DB2
SYS
1
0
0
2
TMP92CF26A
”.
2009-06-25
SMX
0 : OFF
1 : ON
MXEN
R/W
DB1
0
0
0
1

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