TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 441

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

EPx_DATASET_A
EPx_DATASET_B
EPx_DATASET
Note: EPx_DATASETA,B change at 3 clocks of 12MHz after receiving SOF. Write data to FIFO after
EPx_BWR
BWR
SOF
EPx_DATASETA,B are changing.
transaction uses same flow.
renewed. There is no problem in receiving PID if frame data is received with CRC
error, USB sets LOST to STATUS on FRAME register, and exact frame number is
unknown. However, in this case, SOF is asserted and FIFO condition is renewed. If
SOF token is received without transmit and transfer Isochronous in frame, UDC
clears FIFO (X Condition) and sets STATUS to FULL.
The UDC finishes normally by above transaction.
Packet A’s FIFO can be received with next data.
In renewed frame, Packet A’s FIFO interchanges with packet B’s FIFO, and
If SOF token is not received by error and so on, this data is lost because frame is not
5. Below is transaction when SOF token is received from host.
• Change the packet A’s FIFO from X Condition to Y Condition and clear data.
• Change the packet B from Y Condition to X Condition.
• Set frame number to frame register.
• Assert SOF and inform externally that frame is incremented.
• DATASET register clears packet A bit and it sets packet B bit arrangement
• Set STATUS to READY.
loading in present frame.
3clocks (12MHz)
Figure 3.16.9 Isochronous transfer Mode
92CF26A-439
IN
DATA0
IN
DATA0
TMP92CF26A
IN
DATA0
2009-06-25