TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 632

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

A read-
modify-write
operation
cannot be
performed
WDMOD
(1300H)
WDCR
(1301H)
Bit symbol
Read/Write
Reset State
Function
Bit symbol
Read/Write
Reset State
Function
WDT control
1: Enable
WDTE
7
7
1
Figure 3.24.5 Watchdog Timer Control Register
Figure 3.24.4 Watchdog Timer Mode Register
Select detecting time
00: 2
01: 2
10: 2
11: 2
WDTP1
R/W
6
15
17
19
21
6
0
/f
/f
/f
/f
IO
IO
IO
IO
WDTP0
92CF26A-630
5
5
0
B1H: WDT disable code
4EH: WDT clear code
4
4
W
Watchdog timer out control
IDLE2 control
Watchdog timer detection time
Watchdog timer enable/disable control
−
−
00
01
10
11
0
1
0
1
0
1
Others
B1H
4EH
−
Connects WDT out to a reset
Stop
Operation
Disabled
Enabled
3
2
2
2
2
3
15
17
19
21
WDT disable/clear control
/f
/f
/f
/f
IO
IO
IO
IO
(Approximately 819.2 μs at f
(Approximately 3.276 ms at f
(Approximately 13.107 ms at f
(Approximately 52.428 ms at f
Disable code
Clear code
Don’t care
IDLE2
0: Stop
1: Operate
I2WDT
2
2
0
1: Internally
connects
WDT out to
the reset
pin
RESCR
R/W
1
1
0
TMP92CF26A
2009-06-25
IO
IO
Always
write “0”
IO
IO
= 40 MHz)
= 40 MHz)
= 40 MHz)
= 40 MHz)
0
0
−
0