TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 313

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

Match with TB0RG0H/L
Match with TB0RG1H/L
(Value to be compared)
Note: The values that can be set in TBxRGx range from 0001h to 0000h (equivalent to 10000h). If the maximum value
Match with TB0RG0H/L
Match with TB0RG1H/L
(3) 16-bit programmable pulse generation (PPG) output mode
Register buffer 10
(INTTB00 interrupt)
(INTTB01 interrupt)
Figure 3.13.9 Programmable Pulse Generation (PPG) Output Waveforms
000h is set, the match-detect signal goes active when the up-counter overflows.
pulse may be either low active or high active.
by the match of the up counter UC10 with timer register TB0RG0H/L or TB0RG1H/L
and is output to TB0OUT0. In this mode the following conditions must be satisfied.
buffer 10 will be shifted into TB0RG0H/L at match with TB0RG1H/L. This feature
facilitates the handling of low-duty waves.
Square wave pulses can be generated at any frequency and duty ratio. The output
The PPG mode is obtained by inversion of the timer flip-flop TB0FF0 that is enabled
When the TB0RG0H/L double buffer is enabled in this mode, the value of register
TB0RG0H/L
TB0OUT0 pin
(Value set in TB0RG0H/L) < (Value set in TB0RG1H/L)
Figure 3.13.10 Operation of double buffer
Up conter = Q
92CF26A-311
Q
1
1
Q
2
Shift into TB0RG1H/L
Up counter = Q
Q
2
Write into TB0RG0H/L
2
TMP92CF26A
Q
3
2009-06-25