TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 364

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

Example: In case receive data N times
INTSBI interrupt (After transmitting data)
INTSBI interrupt (Receive data of 1st to (N−2) th)
INTSBI interrupt ((N−1) th Receive data)
INTSBI interrupt (Nth Receive data)
INTSBI interrupt (After receiving data)
SBICR1 ← X X X X X X X X
Reg.
End of interrupt
Reg.
End of interrupt
SBICR1 ← X X X 0 0 X X X
Reg.
End of interrupt
SBICR1 ← 0 0 1 0 0 X X X
Reg.
End of interrupt
The process of generating stop
condition
End of interrupt
Note: X: Don’t care
← SBIDBR
← SBIDBR
← SBIDBR
← SBIDBR
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
92CF26A-362
Set the bit number of receive data and ACK.
Load the dummy data.
Load the data of 1st to (N − 2)th.
Not generate acknowledge signal
Load the data of (N − 1)th
Generate the clock for 1bit transmit
Receive the data of Nth.
Finish the transmit of data
TMP92CF26A
2009-06-25