TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 620

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

ADCCLK
(12BFH)
bit Symbol
Read/Write
Reset State
Function
Note1: AD conversion is executed at the clock frequency selected in the above register. To assure conversion
Note2: Don ‘t change the clock frequency while AD conversion is in progress.
f
SYS
accuracy, however, the conversion clock frequency must not exceed 12MHz.
AD conversion speed can be calculated by following.
Conversion speed = 120 × (1/ADCLK)
f
IO
40MHz
30MHz
(f
SYS
7
/2)
Figure 3.23.11 AD Conversion Registers
AD Conversion Clock Setting Register
6
÷1 ∼ ÷7
<ADCLK2:0>
100(f IO /4)
101(f IO /5)
011(f IO /3)
100(f IO /4)
92CF26A-618
5
<ADCLK2:0>
4
ADCLK
10.0MHZ
10.0MHZ
7.5MHZ
8MHZ
Always
write “0”
3
−
0
Select clock for AD conversion
000 : Reserved
001 : f
010 : f
011 : f
AD conversion
ADCLK2
2
0
12 μsec
15 μsec
12 μsec
16 μsec
speed
IO
IO
IO
ADCLK
/1
/2
/3
R/W
ADCLK1
1
0
100 : f
101 : f
110 : f
111 : f
TMP92CF26A
IO
IO
IO
IO
ADCLK0
2009-06-25
/4
/5
/6
/7
0
0