TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 253

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

this bit should be set to “0”.
error address and error bit position has ended.
NDR/B pin of the NAND Flash changes from “busy” (0) to “ready” (1). The interrupt is
enabled when this bit is set to “1” and disabled when “0”.
calculation. For details, see Table3.11.2.
(d) <INTRSC>
(e) <INTRDY>
(f) <STATE3:0>、<SEER1:0>
Hamming codes, they have no meaning.
The <STATE3:0> and <SEER1:0> bits are used only for Reed-Solomon codes. When using
The <INTRSC> bit is used only for Reed-Solomon codes. When using Hamming codes,
This bit is used to enable or disable the interrupt to be generated when the calculation of
The interrupt is enabled when this bit is set to “1” and disabled when “0”.
The <INTRDY> bit is used for both Hamming and Reed-Solomon codes.
This bit is used to enable or disable the interrupt to be generated when the status of the
These bits are used as flags to indicate the result of error address and error bit
92CF26A-251
TMP92CF26A
2009-06-25