TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 517

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

4) FIFO buffer
5) I2SnBUF
6) Share with HALT instruction
use all 128 bytes in the FIFO, data should basically be written in units of 64 bytes
using an INTI2Sn interrupt as a trigger. If data is written to the FIFO without
waiting for an INTI2Sn interrupt or in units other than 64 bytes, interrupts
cannot be generated properly.
bytes, set I2SnCTL<TXEn> to “0” to stop the transmission after writing the data,
then checking that the <TEMPn> flag is set to “1”, and waiting for two I2SWS
periods (i.e., after all the data has been transmitted). In case monaural setting,
make sure that the FIFO is empty by checking the I2SnCTL<TEMPn> flag. Then,
after waiting for four periods of the I2SWS signal (after all the data has been
transmitted), set <TXEn> to “0”.
instructions. Word data load or byte data load instructions cannot be used.
that operate at IDLE1 mode affects to this circuits. If mode is shifted to HALT
mode, set it after I
time to stop completely is necessary before execution of HALT instruction.
The I
If the last set of data, for which an interrupt is not needed, contains less than 64
When writing data to the I2SnBUF register, be sure to use long-word data load
I
When the CPU is shifted to the HALT mode after transmission is stopped, the
It’s time is NOP×10.
2
S circuit is not operated at IDLE1/STOP modes. Therefore, maybe PLL clock
Examples)
Example:
2
S unit is provided with a 128-byte FIFO. Although it is not necessary to
ld
ld
ld
2
S circuit is stopped.
92CF26A-515
(I2SnBUF), xwa; OK
(I2SnBUF), wa;
(I2SnBUF), a;
ld
NOP×10
HALT
(I2SCTL), 0x00
NG
NG
; Stop transmission
TMP92CF26A
2009-06-25