TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 227

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

(b)
(c)
*AP: Auto Precharge
multiplex width is set by SDACR<SMUXW1:0>. Table 3.10.2 shows the relationship
between the multiplex width and low/column addresses.
When the LCDC accesses the SDRAM, the burst length is fixed to full page.
following conditions are satisfied:
Use SDBLS<SDBL5:0> to set the burst length for each HDMA channel.
Pin Name
92CF26A
In access cycles, the A0 to A15 pins output low/column multiplexed addresses. The
When the CPU accesses the SDRAM, the burst length is fixed to 1-word read/single write.
The burst length can be selected for SDRAM read and write accesses by HDMA if the
In other cases, HDMA operation can only be performed in 1-word read/single write mode.
Address multiplex function
Burst length
•
•
A10
A11
A12
A13
A14
A15
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
The HDMA transfer mode is an increment mode.
Transfers are made between the SDRAM and internal RAM or internal I/O.
<SMUXW> = 00
Type A
EA24
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A9
Table 3.10.2 Address Multiplex
<SMUXW> = 01
Row Address
SDRAM Access Cycle Address
92CF26A-225
Type B
EA24
EA25
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
<SMUXW> = 10
Type C
EA24
EA25
EA26
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
Column Address
Row Address
AP *
A10
A1
A2
A3
A4
A5
A6
A7
A8
A9
TMP92CF26A
2009-06-25