TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 377
TMP92xy26AXBG
Manufacturer Part Number
TMP92xy26AXBG
Description
Manufacturer
Toshiba
Datasheet
1.TMP92XY26AXBG.pdf
(768 pages)
Specifications of TMP92xy26AXBG
Package
FPGA228
Rom Types(m=mask,p=otp, F=flash,e=eeprom)
Romless
Rom Combinations
Romless
Ram Combinations
144/288
Architecture
32-bit CISC
Usb/spi Channels
1/1
Uart/sio Channels
2
I2c/sio Bus Channels
1
(s)dram Controller
1
Adc 10-bit Channel
6
Da Converter
-
Timer 8-bit Channel
8
Timer 16-bit Channel
2
Pwm 8-bit Channels
-
Pwm 16-bit Channels
-
Cs/wait Controller
4
Dual Clock
Y
Number Of I/o Ports
136
Power Supply Voltage(v)
3.0 to 3.6
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USBINTFR3
(07F2H)
Prohibit to
read
-modify
-write
USBINTFR2
(07F1H)
Prohibit to
read
-modify
-write
bit Symbol
Read/Write
Reset State
Function
bit Symbol
Read/Write
Reset State
Function
Note: The above interrupt can release Halt state from IDLE2 mode. (IDLE1 and STOP mode cannot be released.)
Note: The above interrupt can release Halt state from IDLE2 mode. (IDLE1 and STOP mode cannot be released.)
Note: The EPx_FULL_A/B and EPx_Empty_A/B flags are not status flags. Therefore, check DATASET register to
determine if the FIFO-status is needed.
•
•
EP1_FULL_A
EP3_FULL_A
R/W
EPx_FULL_A/B:
EPx_Empty_A/B:
R/W
7
0
7
0
When read
When write
(When transmitting)
(When receiving)
(When transmitting)
(When receiving)
This is set to “1” when CPU full write data to FIFO_A/B.
This is set to “1” when UDC full receive data to FIFO_A/B.
This is set to “1” when FIFO become empty after transmission.
This is set to “1” when FIFO becomes empty after CPU reads all data from FIFO.
EP1_Empty_A
EP3_Empty_A
R/W
R/W
6
0
6
When read 0: Not generate interrupt
0
0: Not generate interrupt
1: Generate interrupt
0: Clear flag
1: −
EP1_FULL_B
EP3_FULL_B
R/W
92CF26A-375
1: Generate interrupt
R/W
5
0
5
0
EP1_Empty_B
EP3_Empty_B
R/W
R/W
4
0
4
0
EP2_FULL_A
R/W
When write 0: Clear flag
3
0
3
EP2_Empty_A
R/W
1: −
2
0
2
EP2_FULL_B
R/W
1
0
1
TMP92CF26A
2009-06-25
EP2_Empty_B
R/W
0
0
0
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