TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 503

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

3.18.1
f
f
PLL
SYS
32bit
controlled and made to output independently.
Block Diagram
<CLKS0>
The I
Figure 3.18.1 shows a block diagram for I
I2S0CTL
2
S unit contains two channels: channel 0 and channel 1. Each channel can be
0 1
64-byte FIFO0
<CK07:00>
(2 bytes×32)
<CNTE0>
I2S0CTL
Counter
I2S0C
Write Pointer
Stop
FIFO Control
31
Clock Generator
Figure 3.18.1 I
0 1
<WS05:00>
64-byte FIFO1
Read Pointer
(2 bytes×32)
Counter
Counter
I2S0C
6-bit
8-bit
92CF26A-501
31
2
S Block Diagram
<TXE0,CLKE0>
I2SCKO
I2S0CTL
DIR0, BIT0, WLVL0>
Stop
2
Data Selector
S channel 0.
<DTFMT01:00
Request Signal Output to ADC
(Supported in channel 0 only)
Control
I2SWS
Interrupt
I2S0CTL
<TXE0>
Control
I2S0CTL
<EDGE0>
I2S0CTL
I2SCKO
Invert
INTI2S0
I2S0CKO
I2S0WS
I2S0DO
TMP92CF26A
2009-06-25